When an excessive voltage is applied to an internal circuit of a semiconductor chip due to noise such as static electricity or surge, dielectric breakdown of a gate oxide film and destruction or deterioration of PN junction are caused, so that permanent failure, change in circuit characteristics, or the like of the semiconductor chip occur. In order to prevent the destruction or deterioration of the internal circuit caused by such noise and to realize a semiconductor chip having higher reliability, a protective circuit needs to be provided between a pad and the internal circuit so that an excessive voltage is not applied to the internal circuit even when noise is applied. In the technique described in PTL 1, a polysilicon resistor and a clamp transistor are provided between an input pad and an internal circuit. When an excessive voltage is applied to the pad, the clamp transistor breaks down or snaps back to a low resistance state, and thus, a current flows from the pad to the ground terminal through the polysilicon resistor and the clamp transistor. At this time, most of the energy of noise is absorbed by the polysilicon resistor, and the voltage applied to the internal circuit is clamped to a certain value or less, so that it is possible to prevent the above-mentioned element destruction and deterioration in characteristics.